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Intel Unveils New Tools in Its Advanced Chip Packaging Toolbox

  News: This week's Semicon West in San Francisco, Intel Engineering leaders provided an update to the advanced Intel packaging opportunities, and presented new building blocks, including the innovative emib and folding together and use a new connection technology (ODI). Combined with world-class processing technology Intel the ability to unlock new packaging innovations customers and delivers computer systems of tomorrow.   smoothtechi "Our vision is to develop the technology leadership technology for connecting chips and Chaklets in a package to match the functionality of a monolithic system, en-chips. Heterogeneous our approach provides unprecedented flexibility architects chip for mixing and combining IP blocks and process technology using different memory elements, and input / output of a new device form factors. Intel vertically integrated structure provides an advantage in an era of heterogeneous integration, which gives us an unparalleled ability to coordinate the ar

Intel Unveils New Tools in Its Advanced Chip Packaging Toolbox

 

News: This week's Semicon West in San Francisco, Intel Engineering leaders provided an update to the advanced Intel packaging opportunities, and presented new building blocks, including the innovative emib and folding together and use a new connection technology (ODI). Combined with world-class processing technology Intel the ability to unlock new packaging innovations customers and delivers computer systems of tomorrow.  smoothtechi

"Our vision is to develop the technology leadership technology for connecting chips and Chaklets in a package to match the functionality of a monolithic system, en-chips. Heterogeneous our approach provides unprecedented flexibility architects chip for mixing and combining IP blocks and process technology using different memory elements, and input / output of a new device form factors. Intel vertically integrated structure provides an advantage in an era of heterogeneous integration, which gives us an unparalleled ability to coordinate the architecture, process and packaging to offer leading products. "

-Babak Sabi, corporate vice president of Intel, the Assembly and the development of testing technology

Why it's important: packing chips has always played a crucial role, if it is unrecognizable in the electronics supply chain. As a physical interface between the processor and the motherboard package provides a landing zone for electrical signals and power source of the chip. As the electronics industry is converted into data-oriented data, advanced packaging will play a much greater role than the one in the past.  mucommucation

More than just the final step in the manufacturing process, the packaging becomes a catalyst for product innovation. The improved packaging techniques allow the integration of different computational engines in several processing techniques, with the same performance parameters to one dying, but using the platform, which is much higher than the matrix size limit integration only matrix. These technologies improve performance, power and area at the product level, increasing rethinking complete system architecture.

What are the upgrade Intel: Intel is a leader in advanced packaging technology, with current offerings, covering 2D and 3D approaches? In Semichon West Intel introduced three new technologies that will open up a new dimension in product architecture:  appleinfocom

CO-EMIB: Intel Emib and electo Technologies advantage of compounds of high density to provide high bandwidth at low power, to the input / output density to or better than the competitive approaches. The new joint company's technology allows you to connect even more computing power and performance. CO-EMIB allows to interlock two or more elements substantially performance single chip. And designers can also connect analogues, memory and other tiles with very high capacity and very low power.

ODI: Omnideenedal Interconnection provides even more flexibility for communication between Chublets in the package. Upper chip can communicate with other horizontally Chublets, similar to Emib. You can also communicate vertically with silicone VIAS (TSV) based on the following grounds, similar resistance. ODI and takes advantage of large vertical road to ensure the delivery of energy to the upper matrix substrate directly from a pouch. Much more than the traditional TSV, larger roads have less resistance, providing a more reliable delivery of energy at the same time with greater bandwidth and low latency, enabled through stacking. At the same time, this approach reduces the amount of TSV, required at the bottom of a base, releasing more active areas for transistors and optimization matrix size.  computerlg

MDIO: Construction of its advanced interface (AIB) PHY-level relationship, Intel described new MATRIX interface for skills called MDIO. The technology allows a modular approach to system design with a library of IP blocks Chiple. MDIO provides better power efficiency, and more than double the speed and density of the passing bandwidth offered by AIB.

Together these technologies are complementary tools toolbar powerful. In conjunction with the Intel technology processes they form the basic palette for creation of chip architects, giving them the freedom to dream of new products.  smarttechnofy

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