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Showing posts from March, 2022

Intel Unveils New Tools in Its Advanced Chip Packaging Toolbox

  News: This week's Semicon West in San Francisco, Intel Engineering leaders provided an update to the advanced Intel packaging opportunities, and presented new building blocks, including the innovative emib and folding together and use a new connection technology (ODI). Combined with world-class processing technology Intel the ability to unlock new packaging innovations customers and delivers computer systems of tomorrow.   smoothtechi "Our vision is to develop the technology leadership technology for connecting chips and Chaklets in a package to match the functionality of a monolithic system, en-chips. Heterogeneous our approach provides unprecedented flexibility architects chip for mixing and combining IP blocks and process technology using different memory elements, and input / output of a new device form factors. Intel vertically integrated structure provides an advantage in an era of heterogeneous integration, which gives us an unparalleled ability to coordinate the ar

Intel Unveils New Tools in Its Advanced Chip Packaging Toolbox

  News: This week's Semicon West in San Francisco, Intel Engineering leaders provided an update to the advanced Intel packaging opportunities, and presented new building blocks, including the innovative emib and folding together and use a new connection technology (ODI). Combined with world-class processing technology Intel the ability to unlock new packaging innovations customers and delivers computer systems of tomorrow.   smoothtechi "Our vision is to develop the technology leadership technology for connecting chips and Chaklets in a package to match the functionality of a monolithic system, en-chips. Heterogeneous our approach provides unprecedented flexibility architects chip for mixing and combining IP blocks and process technology using different memory elements, and input / output of a new device form factors. Intel vertically integrated structure provides an advantage in an era of heterogeneous integration, which gives us an unparalleled ability to coordinate the ar

Intel announces node renaming and roadmap to the Angstrom era

  The General Director of Intel Pat Gelsinger organized the global "Intel accelerated" last night last night. There are numerous outstanding aspects of the event for discussion, and in our title you can see that Intel announced plans for the new name of the node name, together using the route map to 2025+. Other interesting titbacks were on topics; Two new process technologies (RivBonfet and PowerVIA), a manual declared in 3D packaging (Omni Fover and Fover Rights Direct), and the Progress News for Intel Foundry Services (IFS) with Qualcomm is announced as the first important client. No later than ADO, consider a new roadmap built above (click to enlarge). To the left, you can see where Intel is now, with pieces of surfaces of 10 nm, created by the mass. In his recent income statement, he said that its volume of 10 nm exceeded 14 nm to the above, so correctly present the current state with this node. Superfine Intel improved 10 Nm was going to come on, and the processors